Management and Application of Power Supply

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Title: Loop Analysis - With Example of TIA

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Power Supply is the most important component in all electric systems. Generally, in one system there’ll be multiple supplies. For example in an ADC an analog voltage 5V and a digital supply 3.3V might be required. The most widely used topologies are DC-DC converter (buck-boost) and low dropout regulator (LDO).

1. Buck Converter

Buck is used to generate a lower voltage supply.

Classical Buck Topology

When the switch is on, supplies energy to the inductor, and the current flows through the inductor and the load to ground. When the switch is off, since the current in the inductor cannot change abruptly, the current flows through the inductor, the load, and the diode. The diode is necessary here because it should be cut-off when the switch is on to prevent a short circuit but should turn on when the switch is off to provide a loop for the inductor, called a freewheeling diode.

When the switch is on,

and when the switch is off,

If we turn on and off the switch at a certain frequency with a duty ratio of , the can be estimated as a linear variation in a small time interval.

Combine and solve:

Since , the buck topology can only be used to decrease the voltage within the positive voltage range.

Next, let’s analyze the operating phases. During , the closed switch connects to the circuit, forming the charging loop. stores energy in the inductor while simultaneously charging the output capacitor and supplying the load, which causes a slight linear increase in the inductor current. Conversely, during , the switch opens, and the inductor, output capacitor, and diode constitute the freewheeling loop (or output loop). The inductor delivers its stored magnetic energy to the output stage to sustain , causing the inductor current to ramp down. Hence, if you have an oscilloscope with a very large sampling rate, you will measure the output like this:

Ripple of Buck output

On the oscilloscope you can see some unexpected AC components, whose frequency is approximately the same as the switching frequency. This AC component is called ripple. Ripple is a primary drawback of the Buck converter (and the Boost in the following section). Clearly, faster switching produces ripple with smaller amplitude but higher frequency, while slower switching produces ripple with lower frequency but larger amplitude.

Another significant drawback is the electromagnetic interference (EMI). During , current flows from the input decoupling capacitor (), through the switch, the inductor, and into the output capacitor () and the load. Conversely, during , the switch opens, forcing the inductor current to pull the switching node negative until the freewheeling diode turns on. Current then circulates strictly from the diode, through the inductor, and into and the load. While the current flowing through the inductor, , and the load is continuous and only ramps up and down smoothly, the current flowing through the input path and the diode path snaps instantly between zero and full load current during every switching transition. Therefore, the loop formed strictly by the input capacitor (), the high-side switch, and the freewheeling diode contains the discontinuous, high- pulsating currents, defining it as the critical Hot Loop.

According to Faraday’s law of induction, an electromotive force (EMF) is induced across the parasitic inductances by this fast-varying current:

If the hot loop has a large physical area, the parasitic inductance within the traces acts as a loop antenna, generating strong radiated magnetic fields and severe high-frequency voltage ringing at the switching node. To effectively suppress this EMI at the source, , the switch, and the diode must be placed immediately adjacent to one another on the same layer of the PCB. Furthermore, the connections between these three components should be routed using short, exceptionally wide traces or copper pours to squeeze the loop area as close to zero as possible, while ensuring a solid, unbroken ground plane rests directly beneath this loop on the immediate next layer to provide a tight return path that cancels out the magnetic fields.

From the perspective of power efficiency, the main energy dissipation of a buck converter is dominated by conduction losses due to the parasitic resistances of the components (like the inductor’s DC resistance and PCB trace resistance) and switching losses incurred during the turn-on and turn-off transitions. Because these parasitic losses are relatively low compared to the total throughput, the efficiency of a practical Buck converter can easily reach approximately 90%.

2. Boost Converter

Unlike a buck converter, a boost converter can only be used to increase the voltage.

Classical Boost Topology

Similarly, during , supplies energy to the output capacitor, maintaining the output voltage to be stable.

During , is isolated by the switch path (short with ground). The output voltage is maintained by the output capacitance. And the input source supplies energy to the inductor

Solve

Similarly to the buck converter, a boost converter also suffers from ripple and EMI. In the boost circuit, the loop -inductor-switch loop is called input loop, and the switch-diode-output capacitor is called output loop. In the input loop the variation of current is suppressed by the inductor, while the output loop has nothing to suppress. Hence, the output loop dominates the EMI. So in PCB layout the output capacitor should be placed as closer to the leads as possible to minimize the physical area of the output loop.

If you need a negative voltage but your input is a single positive one, you need the buck-boost.

Classical Buck-Boost Topology

You can easily recognize the input and output loops. In the input loop

In the output loop

Solve

You still failed to escape from the disturbance of ripple and EMI.

3. Application with MOS

In most integrated DC-DC converter the switch and diode are both replaced with MOSFETs. Another control logic applies PWM waves on the gates of the two MOS’s. Generally, the MOS replacing the switch is called “high-side MOSFET”, while the one replacing the diode is called “low-side MOSFET”.

A combined circuit is displayed below

Combined Buck-Boost Circuit

Conduct Q1 and cut Q2, Q3 serves as the switch and Q4 serves as the diode, the circuit serves as a boost. And when Q3 on, Q4 off, it becomes a buck. The chips sold on the market (buck or boost only) contains only two of the MOS’s.

Buck converter structure sold in market

Two critical pins are designated as SW (Switching Node) and FB (Feedback) respectively. The SW pin denotes the power node between the high-side and low-side MOSFETs, where the external power inductor must be connected. The FB pin connects back to the internal control logic module to monitor the real-time output voltage. In most buck and boost converters, an integrated control module automatically regulates the switching frequency and duty ratio based on this feedback signal to maintain a stable output.

A typical example is TPS54302, a buck converter developed by TI. In the datasheet, TI has provided a well-designed application schematic.

Application example of TPS54302

All pins except BOOT have been analyzed before. This pin manages to solve a critical problem: when the high-side MOSFET turns on, the input voltage flows to its source terminal, making the source voltage approach the input voltage. Hence, to keep the high-side MOSFET fully enhanced, the gate must be applied a voltage greater than . However, the input voltage is typically the highest voltage available in the entire system. To overcome this limitation, the bootstrap capacitor () is utilized to generate a higher voltage supply.

When the high-side MOSFET turns off and the low-side MOSFET turns on, the lower terminal of is pulled down to GND through the SW node, allowing the internal power supply to charge until the voltage across the capacitor reaches the supply voltage. After a short period, when the high-side MOSFET turns on and the low-side MOSFET turns off, the lower terminal of is lifted to the SW node voltage, which approaches . Since the voltage across the capacitor cannot change abruptly, the voltage at the BOOT pin is boosted up to approximately , providing a sufficiently high voltage to power the gate driver of the high-side MOSFET.

The reason why PMOS is not used here is that PMOS occupies larger area under the same performace because the mobility of electrons is twice or three times than holes.

Bootstrap circuit

4. Low Dropout Regulator (LDO)

LDO is another type of power management circuit, only applicable in decreasing the voltage. LDO can be regarded as a variable resistance with a feedback loop. It uses an error amplifier and an NMOS to perform this function.

Classical LDO Topology

LDO has no switching inside the chip, so there is almost no switching ripple. Instead, the regulation is implemented by a continuous negative feedback loop. Inside the chip, an error amplifier continuously monitors the scaling output voltage from the feedback resistors and compares it with an internal reference voltage. If the feedback voltage slightly exceeds the reference, the error amplifier seamlessly adjusts the gate voltage of the power MOSFET (such as an NMOS pass element), smoothly increasing its equivalent channel resistance. This continuous adjustment increases the voltage drop across the MOSFET, immediately pulling the output voltage back down to the target value. Through this analog linear feedback process, the output voltage is perfectly stabilized without introducing high-frequency switching noise. Since the feedback resistors are typically placed outside the chip, we can select their values to configure the desired output voltage.

We denote the resistor between FB and as and another as . We should equal the equilibrium voltage at pin FB to the internal reference voltage, so

Reverse the equation,

Note that the MOSFET on the main power path requires a minimum voltage headroom to remain in its active conductive region, which determines the minimum input-to-output voltage difference known as the dropout voltage. You can find this critical parameter in the datasheet.

One inherent drawback of LDOs is their low efficiency under large voltage gaps. Inside the chip, the dominant energy loss does not stem from the quiescent current of the control circuitry, but rather from the power dissipation across the internal pass MOSFET itself. Since the full load current passes through this transistor, it drops the excess voltage () and converts that energy entirely into heat. Outside the chip, the feedback resistors provide another path from the output voltage to ground. However, engineers purposely select large resistance values to avoid excessive current loss on this path while providing high impedance for precise voltage sensing, making the feedback loop loss negligible.

Since the feedback current and internal quiescent current are small enough to be neglected, the input current is practically identical to the output current. Thus, the efficiency of an LDO is tightly bounded by the voltage ratio:

The rest of the electrical energy is entirely dissipated as heat within the package. Therefore, LDOs are not suitable for applications with a large dropout voltage combined with high load currents, as the excessive thermal stress can rapidly overheat the device.

Despite the efficiency penalty, LDOs outperform buck converters in nearly all other performance metrics, offering ultra-low output ripple, zero switching EMI, and excellent transient response. Consequently, in practical power system designs, they are frequently combined to achieve both high efficiency and high purity. For instance, if the system requires a clean, low-noise 12V supply from a lower input power source, a boost converter is first applied to efficiently raise the voltage to around 13V or 14V. Then, an LDO is cascaded to drop and precisely stabilize the voltage to 12V. This architecture allows the LDO to effectively reject the high-frequency switching ripple inherited from the boost converter, providing an exceptionally quiet and high-quality power rail for sensitive analog circuits.

Reference

[1] B. Razavi, “The Design of An LDO Regulator,” IEEE Solid-State Circuits Magazine, vol. 14, no. 2, pp. 7-11, Spring 2022, doi: 10.1109/MSSC.2022.3164746.
[2] TPS54302 4.5V to 28V Input, 3A Output, EMI-Friendly Synchronous Step-Down Converter Datasheet, Texas Instruments Incorporated, Doc. No. SLVSDG6C, May 2016, Revised March 2026.
[3] “Considerations on bootstrap circuitry for gate drivers,” STMicroelectronics, Geneva, Switzerland, Application Note AN5789, Rev. 1, Mar. 2022.